The present invention relates to integrated circuit chip carrier devices, and, more particularly, to an apparatus and method for making electrical connection with a mother electronics board or other electronic assembly.
In the past, integrated circuit chip packages (or carriers) have employed pin and socket pairs to electrically connect the input/output ports of the integrated circuit with the input/output ports of the mother board or recipient electronic assembly. These pin and socket pairs have generally consisted of batch fabricated pins brazed to electrical contacts on the side of the chip carrier substrate, as well as matching batch fabricated socket receptors which are mounted to the recipient electronic assembly. In a more recent technology, the "Pin Grid Array" technology, individual pin and socket pairs have been fabricated and soldered to input/output ports of the chip carrier and mother board, respectively.
Both of these designs have the disadvantages that they require large substrates for support of the interconnectors, and that, as a result, the chip carrier must be substantially larger than the integrated circuit itself. These chip carriers have the further disadvantage that it is difficult to obtain accurate and repeatable height control of the top surface of the integrated circuit. This is particularly critical where electro-optical detection devices are mounted on the integrated circuit, and accurate height control is necessary to ensure proper focusing of the device. Pin connectors have the additional disadvantage since it is not possible to make any significant lateral adjustment in position once the pin positions have been determined.
Accordingly, it is a primary object of the present invention to provide an improved interconnect mechanism for an integrated circuit chip carrier which is compact in size, easily reconnectable, and which provides an accurate and reproducible means of integrated circuit height control and lateral position.